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Related Events

  • 2008 | Somerset Design Center, Freescale Semiconductor, Inc.
    Low Power/Area Branch Prediction Using Complementary Branch Predictors
  • 2007 | Electrical and Computer Engineering Departmental Seminar
    Analyzing and Improving the Statistical Rigor of Computer Architecture Simulation
    University of Florida
  • 2007 | Electrical and Computer Engineering Departmental Seminar
    “Analyzing and Improving the Statistical Rigor of Computer Architecture Simulation
    Northwestern University

Related Publications

  • May/June 2010 | IEEE Micro
    Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
  • 2007 | IEEE Transactions on Computers
    Speed and Accuracy Trade-offs in Microarchitectural Simulations
  • Nov./Dec. 2007 | IEEE Micro
    Where Does Security Stand?: New Vulnerabilities versus Trusted Computing

Joshua J. Yi, Ph.D., focuses his practice on patent litigation matters.

Dr. Yi has seven years of industry work experience as a former engineer for Freescale Semiconductor, Inc. (formerly Motorola’s Semiconductor Products Sector), Retek, Inc. (now part of Oracle Corporation), Summit Design, Inc., and Fisher-Rosemount, Inc. (now part of Emerson). His diverse technical background includes experience with computer architecture, parallel computer architecture, simulation methodology, performance analysis and optimization, low power microprocessor design, benchmarking and workload characterization, fault and variation tolerant microprocessor design, design of very large scale integrated (VLSI) digital circuits, computer-aided design of digital circuits, embedded system design, system-on-a-chip (SoC) design, semiconductor materials and design, semiconductor fabrication, digital signal processing, analog circuit design, neural networks, and temperature and pressure transmitters and sensors. He has published over thirty peer-reviewed book chapters, journal papers, and conference publications.

Dr. Yi was a Dechert summer associate in 2011. His prior experience also includes serving as a judicial intern for the Honorable Lee Yeakel of the Western District of Texas, Austin Division.

Significant Representations

  • Represented a client in a patent litigation case involving Display Data Channel Command Interfaces (DDC/CI) for computer monitors and televisions.
  • Represented a client in two patent litigation cases regarding digital television technology.
  • Represented a client in a patent litigation case involving Digital Subscriber Line (DSL) telecommunication technology.
  • Represented a client in a patent litigation case involving encryption in Wi-Fi telecommunication technology.

Education

University of Minnesota, B.S., 1996, Dean’s List
University of Minnesota, M.S., 1999
University of Minnesota, Ph.D., Electrical Engineering, 2003
The University of Texas at Austin, J.D., 2012, Summer Staff Editor of the Texas Intellectual Property Law Journal, Associate Editor and Technical Editor of the Texas Review of Law and Politics

Court Admissions

United States Patent and Trademark Office
United States District Court for the Eastern District of Texas
United States District Court for the Western District of Texas
United States District Court for the Northern District of Texas
United States District Court for the Southern District of Texas
United States Bankruptcy Court, Southern District of Texas
United States Bankruptcy Court, Northern District of Texas
United States Bankruptcy Court, Eastern District of Texas

Bar Admissions/Qualifications

Texas

Memberships

Institute of Electrical and Electronics Engineers (IEEE) , Senior Member
IEEE Computer Society
Co-founder and co-organizer of the Workshop on Computer Architecture Research Directions (CARD), 2007-2015
Co-founder and co-organizer of the Workshop on Modeling, Benchmarking, and Simulations (MoBs), 2005-2009
Co-guest editor of the special issue “Computer Architecture Simulation and Methodology,” IEEE Micro, July/Aug. 2006